Integrated circuits are often designed to incorporate scan test circuitry that facilitates testing for various internal fault conditions. Such scan test circuitry typically comprises scan chains, which are chains of flip-flops that are used to form serial shift registers for applying test patterns at inputs to combinational logic of the integrated circuit and for reading out the corresponding results.
In one exemplary arrangement, an integrated circuit with scan test circuitry may have a scan shift mode of operation and a functional mode of operation. A flag may be used to indicate whether the integrated circuit is in scan shift mode or functional mode. In the scan shift mode, the flip-flops of the scan chain are configured as a serial shift register. A test pattern is then shifted into the serial shift register formed by the flip-flops of the scan chain. Once the desired test pattern has been shifted in, the scan shift mode is disabled and the integrated circuit is placed in its functional mode. Internal combinational logic results occurring during this functional mode of operation are then captured by the chain of scan flip-flops. The integrated circuit is then once again placed in its scan shift mode of operation, in order to allow the captured combinational logic results to be shifted out of the serial shift register formed by the scan flip-flops, as a new test pattern is being scanned in. This process is repeated until all desired test patterns have been applied to the integrated circuit.
As integrated circuits have become increasingly complex, scan compression techniques have been developed which reduce the number of test patterns that need to be applied when testing a given integrated circuit, and therefore also reduce the required test time. However, the use of high levels of scan compression can adversely impact diagnostic resolution, that is, the ability to attribute a particular failure to an exact fault or set of faults within the combinational logic. As a result, when using scan compression, a tradeoff exists between compression level and diagnostic resolution. Additional details regarding compressed scan testing are disclosed in U.S. Pat. No. 7,831,876, entitled “Testing a Circuit with Compressed Scan Subsets,” which is commonly assigned herewith and incorporated by reference herein.
Many integrated circuits include multiple distinct circuitry cores. For example, an integrated circuit utilized in a hard disk drive (HDD) application may comprise a system-on-chip (SOC) with multiple cores, including a read channel core and at least one other core. A problem that arises is that the read channel core is typically very large, which makes it difficult to accommodate both the read channel core and the rest of the SOC in the same test mode. As a result, in conventional arrangements, a significant number of functional paths going into and out of the read channel may remain untested. In such arrangements, wrapper cells may be used to form a scan chain around each of one or more cores in order to allow interconnect paths between those cores to be tested. However, conventional techniques for implementing wrapper scan chains are generally not area or timing efficient, and therefore may unduly increase the size and cost of the integrated circuit while also adversely impacting its performance.
It should be noted that the above problem is not limited to integrated circuits that include SOCs with read channel cores. Similar issues can arise in a wide variety of other types of integrated circuits that comprise multiple distinct circuitry cores.